1. Field of the Invention
The present invention relates to a memory device employing memory cells each including a variable-resistance storage element which has a resistance changing in accordance with a voltage applied to the variable-resistance storage element and is connected in series to an access transistor, and relates to a method for operating the memory device.
2. Description of the Related Art
There has been already known a memory device employing memory cells each including a variable-resistance storage element which has a resistance changing due to injection of conductive ions into an insulation film of the variable-resistance storage element or due to extraction of such ions from the insulation film. For more information on this memory device, the reader is suggested to refer to a document such as K. Aratani etc., “A Novel Resistance-type memory with High Scalability and Nanosecond Switching,” Technical Digest IEDM 2007, pp. 783-786.
The variable-resistance storage element has a laminated structure constructed by creating a conductive-ion supplying layer and the insulation film cited above between two electrodes of the variable-resistance storage element.
Every memory cell employs a variable-resistance storage element and an access transistor which are connected to each other in series between first and second common lines drivable in an active matrix driving operation. Since the memory cell employs a transistor (T) and a variable-resistance resistor (R), the memory cell is referred to as a 1T1R-type memory cell.
The memory device employing 1T1R-type memory cells is referred to as a ReRAM.
In the ReRAM, the resistance of a variable-resistance storage element is used to indicate a state in which data has been stored in the variable-resistance storage element or a state in which data has been erased from the variable-resistance storage element. That is to say, the resistance of a variable-resistance storage element indicates the value of data stored in the variable-resistance storage element. A data write operation to store data in a variable-resistance storage element and a data erase operation to erase data from a variable-resistance storage element can be carried out by applying a pulse having a small width of the order of some ns (nanoseconds) to the variable-resistance storage element. Thus, since the ReRAM is an NVM (non-volatile memory) capable of operating at as high a speed as a RAM (Random Access Memory), the ReRAM draws much attention.
In order for the ReRAM to serve as a substitute for a flash memory which is the contemporary NVM of the FG (Floating Gate)_NAND type, however, it is necessary for the ReRAM to surmount several barriers. Some of the barriers are requirements for a high-speed verify sub-operation and high-speed inhibit control which need to be carried out in the data write and erase operations as described below. In this specification of the present invention, in case it is not necessary to distinguish the data write operation and the data erase operation from each other, both the data write and erase operations are referred to as a data update operation which is a generic technical term for them.
In the data update operation, a verify sub-operation is carried out after a data transition sub-operation. The data-transition sub-operation is carried out prior to the verify sub-operation by application of an update (that is, write or erase) pulse to a variable-resistance storage element in order to update data which has been stored in the variable-resistance storage element. On the other hand, the verify sub-operation is carried out in order to determine whether or not the data serving as an update has been stored in a variable-resistance storage element correctly by the application of the update pulse to the variable-resistance storage element.
The inhibit control is executed right after the verify sub-operation in order to assure that the data update operation has been carried out correctly, that is, in order to prevent (or inhibit) the data update operation from resulting in incorrect data stored as a result of the data update operation. That is to say, the inhibit control is control executed in order to avoid a transfer of unintended data as an update to the variable-resistance storage element of the memory cell in the data update operation which is carried out to gradually update (that is, write or erase) data stored in the variable-resistance storage element by repeating the data transition sub-operation consecutively a plurality of times. To put it in detail, if a determination result produced in the verify sub-operation indicates that data serving as an update has been transferred to the variable-resistance storage element correctly, the inhibit control is control executed in order to prevent an additional update pulse from being applied to the variable-resistance storage element and another data transition sub-operation from being carried out as a part of the data update operation. If the determination result produced in the verify sub-operation indicates that data serving as an update has not been transferred to the variable-resistance storage element correctly, on the other hand, the inhibit control is control executed so as to apply an additional update pulse to the variable-resistance storage element in order to carry out another data transition sub-operation as a part of the data update operation to update data correctly.
The control described above is a method adopted by a number of NVMs.
As is obvious from the above description, a data update operation includes a data transition sub-operation, a verify sub-operation and inhibit control. The technical term ‘verify sub-operation’ is deliberately used in this specification of the present invention to imply a data read sub-operation carried out after a data transition sub-operation in order to distinguish the data read sub-operation carried out after a data transition sub-operation from a normal data read operation.
Much like other NVMs, the ReRAM also allows high operation reliability to be implemented by executing inhibit control right after each verify sub-operation in accordance with the determination result produced in the verify sub-operation.
In the ReRAM, the direction of a current flowing in a data read operation to read out data from the variable-resistance storage element is the same as the direction of a current flowing in a data update (that is, write or erase) operation. By the way, a disturbance is a fault caused by mistakenly updating data stored in the variable-resistance storage element during a data read operation. Thus, in order to prevent the disturbance from occurring in a data read operation, it is necessary to read out data in the data read operation from the variable-resistance storage element of the memory cell employed in the ReRAM by applying a deliberately decreased voltage to the variable-resistance storage element. That is to say, in general, the inhibit control of the data update operation is executed by changing the voltage applied to the variable-resistance storage element to a magnitude different from that used in the data read operation.
There has been disclosed a method for carrying out a verify sub-operation preceding inhibit control which is executed by changing the voltage applied to the variable-resistance storage element. In accordance with this method, an electric potential applied to a bit line BL (that is, an electric potential appearing on the bit line BL) is once initialized after application of an update pulse in order to again apply a BL (bit line) voltage optimum for the verify sub-operation to the bit line BL. For more information on this method, the reader is suggested to refer to a document such as Japanese Patent Laid-open No. Hei 5-144277 (hereinafter referred to as Patent Document 1).
That is to say, in order to carry out the verify sub-operation, the electric potential appearing on the bit line BL is initialized in order to change a voltage applied to the variable-resistance storage element of the NVRAM from the magnitude of the update pulse for the data update operation to a magnitude optimum for the verify sub-operation.
In addition, in accordance with the method disclosed in Patent Document 1, the verify sub-operation and the inhibit control are executed independently of each other for each column (or each sense amplifier). Thus, the method is suitable for parallel operations.
There has been disclosed a method in accordance with which residual electric charge remaining on the bit line BL after application of an update pulse is discharged through the memory cell and a voltage change obtained as a result of the electrical discharge process is detected. For more information on this method, the reader is suggested to refer to a document such as Japanese Patent Laid-open No. 2007-133930 (hereinafter referred to as Patent Document 2).
In accordance with the method disclosed in Patent Document 2, the verify sub-operation is carried out without waiting for time to lapse since the application of an update pulse having a relatively high voltage. That is to say, the verify sub-operation is carried out by applying a relatively high voltage, which may cause a read disturbance, to the variable-resistance storage element of a memory cell.
However, such a high voltage is applied to a memory cell only in a verify sub-operation and a disturbance stress matches an update stress. Thus, no problem is raised.
In addition, since the verify sub-operation is carried out without waiting for time to lapse since the application of an update pulse, the verify sub-operation can be completed in a short period of time.
On top of that, a voltage for electrically pre-charging the bit line BL in a verify sub-operation is high, the S/N (signal to noise) ratio can be sustained at a high value. Thus, the stability of the verify sub-operation is good.